Cadence Design Systems (NASDAQ:CDNS) is benefiting from multiple artificial intelligence-related trends across chip design, electronic design automation and system simulation, Richard Gu, vice president of investor relations at Cadence, said during an investor conference discussion.
Gu described Cadence as a company founded “by engineers for engineers” that plays a “pivotal and foundational role” in the semiconductor ecosystem. He said the company’s portfolio includes IP, EDA and system design analysis tools used to design advanced chips and electronic systems, including AI accelerators, smartphones, autonomous vehicles and aerospace systems.
AI Seen as a Major Growth Driver
Gu said Cadence views AI through two primary lenses: “design for AI” and “AI for design.” On the first, he said Cadence technology is used by major semiconductor companies, hyperscalers and other customers to design AI chips. On the second, he said Cadence is applying reinforcement learning and agentic AI to its own products.
As an example, Gu cited Cadence’s ChipStack product, saying Nvidia CEO Jensen Huang discussed its use and said it delivered more than a 40-times productivity improvement for Nvidia’s engineering team during Computex in Taiwan. Gu said that was a “strong validation” of Cadence’s product roadmap in agentic AI.
Gu pushed back on the idea that AI could reduce the need for Cadence tools. He said Cadence’s core software is grounded in “immutable ground truths” such as physics and mathematics, and that customer relationships are deeply embedded through frequent R&D-level interaction.
He said agentic AI could expand Cadence’s total addressable market by shifting more R&D spending from labor toward automation and tools. According to Gu, customer design demand is rising much faster than engineering supply, making automation increasingly necessary.
Agentic AI Monetization Model
Gu said Cadence is considering a monetization model for agentic AI that combines subscription and consumption-based pricing. He compared the model to a car rental, with a base subscription and additional usage-based charges.
He said Cadence views AI agents as “virtual engineers” and would price them based on the value of what a human engineer can do, not like low-cost large language model tokens. Gu said such agents can work around the clock and explore more design options, which could also increase usage of Cadence’s underlying EDA tools.
Gu also referenced Huang’s comment at CadenceLIVE that he would be willing to spend 50% of a human engineer’s cost on tokens. Gu said that implies a potential opportunity equal to roughly one-third of the R&D budget, compared with EDA’s current share of about 11% to 12%.
IP Business and Foundry Expansion
Gu said Cadence’s IP business is growing well above the market for the third consecutive year and is expected to grow above 23% this year. He said Cadence historically underinvested in IP while focusing on strengthening EDA, but AI has changed the opportunity set.
AI chip architectures are increasingly disaggregated, Gu said, with multiple chips connected through chiplets or 3D IC designs. That is driving demand for higher-value IP such as UCIe, PCIe, SERDES, HBM and DDR memory-related technologies.
Gu also said Cadence is benefiting from foundry ecosystem expansion. He cited collaboration with TSMC, Samsung and Arm, as well as a recently announced collaboration with Intel on its 14A process. He also referenced Rapidus in Japan and comments by Elon Musk about “Terafab” as examples of broader foundry diversification that could create more opportunities for Cadence.
Competition and System Design Analysis
Asked about competition, Gu said Cadence is “very strong” and gaining share across the board. He described EDA as largely a duopoly between Cadence and Synopsys, and said Cadence differentiates through a product- and R&D-centric strategy.
Gu said Cadence is strong in analog, digital and verification. He called Cadence’s Palladium verification platform the “gold standard,” saying its use of Cadence’s own ASIC is a differentiator.
In system design and analysis, Gu said Cadence is focusing on two areas closely tied to AI: packaging, 3D IC and chiplets near the silicon side, and physical AI applications such as robotics, autonomous driving and drones. He said Cadence’s acquisition of Hexagon’s design and engineering business added Adams and Nastran, two simulation platforms for multibody robotics and related applications. Combined with BETA CAE, Gu said Cadence now has a “full flow” for physical AI simulation.
Capital Allocation and Long-Term Approach
Gu said Cadence does not provide multiyear guidance, but its operating philosophy is to drive double-digit growth, achieve more than 50% incremental margins and use more than 50% of free cash flow for share repurchases. He said the company’s organic core business has incremental margins close to 60%.
On mergers and acquisitions, Gu said Cadence’s first priority is organic investment in R&D. He said the company has no appetite for major transformative deals, but may pursue tuck-in acquisitions when the right asset or talent is available at an attractive price.
Gu said Cadence’s portfolio is “fairly complete and comprehensive,” and that the company’s focus remains on building the best products to support customer innovation.
About Cadence Design Systems (NASDAQ:CDNS)
Cadence Design Systems, Inc (NASDAQ: CDNS) is a global provider of electronic design automation (EDA) software, hardware and intellectual property used to design and verify advanced semiconductor chips, systems-on-chip (SoCs), printed circuit boards (PCBs) and packaging. Headquartered in San Jose, California and founded in 1988, Cadence serves semiconductor companies, original equipment manufacturers and system designers across the globe, helping customers accelerate design cycles and manage the complexity of modern integrated systems.
The company’s offerings span software tools for digital, custom/analog and mixed-signal design, verification and signoff, as well as solutions for system-level modeling, thermal and signal integrity analysis, and PCB and package design.
